Rick Cattell, SynapticLink.org, last updated 2/1/2012

Additional brain projects and neuroscience projects

Rick Cattell, SynapticLink.org, last updated 2/1/2012

Project

PI

Some co-authors

Seo, Merolla

Lester, Temple, Shapiro

Meier, Ehrlich, Davidson, Bruderle

Bishop, Schurmann, Druckmann, Hill, Hines

Lin, Sridharan, Wittig, Wen, Chandrasekraran

Joshi, Vogelberg, Mallik, Hafliger, Bergh, Yu

Site

IBM Research

Manchester

Heidelberg+

EPFL Switzerland

Stanford

UCSD

Related projects

Earlier Cat Cortex Simulation on Blue Gene and Map of Maquaque Brain

BrainScaleS follow-on 2011

ChipGen tool and courses

NeuroDyn project with fine-grain bio-realism

Overview papers

Merolla et al 2011, Seo et al 2011, Ananthanarayanan et al 2009

Jin et al 2010, Rast et al 2010, Furber and Temple 2007, Brown et al 2010

Schemmel et al 2010, Ehrlich et al 2010

Markram Perspectives, Markram 2006, Wulfram 2009, Hines et al 2008

Boahen 2005, Silver et al 2007, Merolla et a 2007, Lin et al 2006

Joshi 2010, Yu 2010, Yu 2009, Vogelstein 2007, Vogelstein 2004, Genov 2003, Systems list

Other papers

Neuron simulation

Leaky integrate-and-fire neurons on chip implemented in digital hardware, Hebbian or STDP learning in circuit.

Low-power ARM 968 CPUs simulate 1000 neurons each. 18 ARM CPUs with RAM on each chip.

Interconnected analog neuro-morphic ASICs. Claim to emulate same waveforms as neurons on same input. Several hundred “Spikey” chips, each hosts about 100K synapses.

Supercomputer simulates analog processes of neurons and dendrites. Can handle about 100K neurons with BlueGene.

Programmable analog neurocore chip emulates about 1000 neurons. Also building custom ASICs with similar architecture.

HiAER IFAT chips emulate 65,000 neurons. Uses dynamically programmable conductance-like synapses.

Synapse simulation

Array of axons x neurons w/synapses at junctions. SRAM stores weights. AER networking between chips, not yet specified.

Spikes delivered by AER packet network both on-chip and between chips. Simple routers store synaptic connections in RAM tables. Programmable delays.

Novel wiring of uncut wafers; intra-wafer chip connections. HICANN “analog network chip”. Use AER packets inter- wafer?

Message-passing in software with programmed delays. STDP/etc implemented in software as well.

Direct wiring to nearby within neurocore, digital AER messaging for more distant, synaptic addresses stored in RAM.

HiAER-IFAT uses local connections on-chip, tree of FPGA routers for AER inter-chip.

Comments on overall approach

All digital (no analog). Early state at this point, with 256-neuron chip.

Connection info in shared RAM on chip, used for routing; also, each CPU has 100KB RAM.

Led project with other EU sites. 100K times faster than real neurons. PyNN language to define layouts.

Constructing model of 10,000 neurons from rat somatosensory cortical column on “Blue Gene” supercomputer.

Encouraging others to use tools and approach.

HiAER-IFAT scales w/simple neuron model, NeuroDyn is small-scale for more bio-realism.

Main advantage

Utilizes latest IBM chip fabrication. Identical to software emulation, w/higher performance.

Uses and expands on known silicon, architecture, and networking technology. Easy to experiment, all software.

Moderately bio-realistic at neuron level. Some innovation in connectivity. Combines analog and digital effectively.

Most bio-realistic. No new hardware required. Software is easy to change.

Combines best of analog and digital.

Combines best of analog and digital.

Main disadvantage

Axon-neuron crossbar may not scale well? Inter-chip connectivity TBD.

Interconnection problem unsolved: using wires locally, “event packets” with target address/time for longer range?

Expensive simulation.

Limited scalability to date; degree of neuron plasticity unclear.

Can AER router tree handle bandwidth at root?

Other comments

Received substantial DARPA SyNAPSE funding.

Is an ARM CPU overkill to simulate neurons? Could put 1000 simpler CPUs on a chip?

Use “wafer scale integration”: connect chips directly on wafer. Each chip can host 8 neurons with 16K inputs, or 512 neurons with 256 inputs.

Using model of 10K neurons from somatosensory cortex of 2-week-old rat. Model is stochastic based on statistical % connectivity, not the actual connections.

Experimenting with applications of their approach, e.g. analog VLSI Silicon Retina growth cones and Silicon Cochlea.

The papers with Yu are about the Neurodyn chip.

INC co-directors Sejnowski and Cauwenberghs are also at Sauk.

Project

SN Lab & Others

Host

USC

ETH & UZH Zurich

Qualcomm

Sauk

Cornell